Analysis and Design of High Speed Low Power Comparator in ADC

  Abhishek Rai,  B Ananda Venkatesan

the fast growing electronics industry is pushing towards high speed low power analog to digital converters. Comparator is electronic devices which are mainly used in Analog to Digital converter (ADC). In ADC they are used for quantization process, and are mainly responsible for the delay produced and power consumed by an ADC. A high speed low power comparator is required to satisfy the future demands. The circuits presented in this paper are designed using 0.18μm CMOS technology with 1.8v bias voltage and 1-2μA bias current. This paper also discusses the advantage of using programmable hysteresis to the comparators. Tanner EDA environment is used for the design and simulation for the comparator circuits. Comparison of the proposed comparator with existing double tail comparator is performed and the result is discussed in detail.

Keywords- Double Tail Comparator, high speed Analog to digital converter (ADC), hysteresis, Two stage CMOS amplifier, tanner EDA.

Unique Identification Number - IJEDR1401182
Page Number(s) - 1015-1020
Pubished in - Volume 2 | Issue 1 | March 2014
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Abhishek Rai,  B Ananda Venkatesan,   "Analysis and Design of High Speed Low Power Comparator in ADC", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 1, pp.1015-1020, March 2014, Available at :http://www.ijedr.org/papers/IJEDR1401182.pdf