Design And Comparison Of Viterbi Decoder On Spartan-3A (XC3S400A-4FTG256C) and Spartan-3E (XC3S500E-4FT256) Using Verilog

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Paper Details

Paper Title

Design And Comparison Of Viterbi Decoder On Spartan-3A (XC3S400A-4FTG256C) and Spartan-3E (XC3S500E-4FT256) Using Verilog

Authors

Patel Jigar B, Nabila Sheikh

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Abstract

It is well known that data transmissions over wireless channels are affected by attenuation, distortion, interference and noise, which affect the receiver’s ability to receive correct information. Convolutional encoding with Viterbi decoding is a powerful method for forward error detection and correction. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. In this paper, we present a comparison of Two different method for Implementation which is Spartan-3A (XC3S400A- 4FTG256C) Field- Programmable Gate Array and Spartan-3E (XC3S500E- 4FT256) of Viterbi Decoder with a constraint length of 3 and a code rate of 1/2.

Keywords- Convolutional encoder, FPGA, Traceback method, Spartan-3A (XC3S400A- 4FTG256C) Board, Spartan-3E (XC3S500E- 4FT256) , Viterbi decoder

Publication Details

Unique Identification Number - IJEDR1402194
Page Number(s) - 2512-2517
Pubished in - Volume 2 | Issue 2 | June 2014
DOI (Digital Object Identifier) -
Publisher - IJEDR (ISSN - 2321-9939)

Cite this Article

Patel Jigar B, Nabila Sheikh, "Design And Comparison Of Viterbi Decoder On Spartan-3A (XC3S400A-4FTG256C) and Spartan-3E (XC3S500E-4FT256) Using Verilog", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 2, pp.2512-2517, June 2014, Available at :http://www.ijedr.org/papers/IJEDR1402194.pdf

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