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INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH
(International Peer Reviewed,Refereed, Indexed, Citation Open Access Journal)
ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
ASIC Implementation of High Throughput PID Controller
Authors
  Chavan Suyog,  Sameer Nandagave,  P.Arunkumar

Abstract
In this paper we implemented the pipelined Proportional Integral Derivative (PID) controller using the ASIC Implementation. We used Han Carlson adder and pipelined multiplier to design the PID controller which results into the implemented design can be useful to the modern controlling operations which requires low power and improved speed performance. The implemented design is tuned and analyzed with frequency responses for various error coefficients values using the Matlab. The Controller algorithm is simulated and synthesized using Modelsim and Cadence RC Compiler and ASIC Implementation is done with Cadence Encounter tool. The results are compared with the traditional architecture in terms of power, speed and the area.

Keywords- PID, Han Carlson Adder, ASIC
Publication Details
Unique Identification Number - IJEDR1403026
Page Number(s) - 3055-3060
Pubished in - Volume 2 | Issue 3 | Sept 2014
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Chavan Suyog,  Sameer Nandagave,  P.Arunkumar,   "ASIC Implementation of High Throughput PID Controller", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 3, pp.3055-3060, Sept 2014, Available at :http://www.ijedr.org/papers/IJEDR1403026.pdf
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