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INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH
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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Design and Synthesis of Efficient FSM for Master and Slave Interface in AMBA AHB
Authors
  P.Harishankar,  Mr.Chusen Duari,  Mr. Ajay Sharma

Abstract
Nowadays in industry development of Silicon on Chip (SOC) devices with reusable IP cores are given higher priority, the major challenge faced here is to ensure proper lossless communication between these IP cores in SOC device, this can be ensured with the help of standard communication protocols such as AMBA from ARM Ltd. In this paper we design and synthesize efficient Finite State Machine (FSM) for master and slave interface in AMBA AHB. The interfaces are capable of responding to split, retry and error responses during a simple read and write transfer. The AMBA AHB system is designed using Hardware description language such as Verilog using Modelsim tool and synthesized using Xilinx ISE tool.

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Publication Details
Unique Identification Number - IJEDR1403042
Page Number(s) - 3167-3175
Pubished in - Volume 2 | Issue 3 | Sept 2014
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  P.Harishankar,  Mr.Chusen Duari,  Mr. Ajay Sharma,   "Design and Synthesis of Efficient FSM for Master and Slave Interface in AMBA AHB", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 3, pp.3167-3175, Sept 2014, Available at :http://www.ijedr.org/papers/IJEDR1403042.pdf
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