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INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH
(International Peer Reviewed,Refereed, Indexed, Citation Open Access Journal)
ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Analysis of High Speed Parallel Multiplier
Authors
  Manthan J. Trivedi,  Vimal H. Nayak,  Mohmmed G. Vayada

Abstract
This research paper represents the analysis of Advanced Modified Booth Encoder (AMBE) parallel Multiplier with the already invented Booth multiplier and Modified Booth Encoding Multiplier. The existed Booth and Baugh Wooley Multipliers are used for only signed numbers, while array multipliers uses only for unsigned numbers. Modern Computer system needs a very high speed parallel multiplier which is used for signed and unsigned numbers. This multiplier is obtained by extending a sign bit from Modified Booth Encoder and generates an additional partial product. The Carry Save Adder tree (CSA) and Carry Look Ahead Adder (CLA) are used to add all partial products and generates the final product. This multiplier uses for both signed and unsigned numbers so total chip area reduces and power reduces as well. The Advanced Modified Booth Encoding parallel multiplier is simulated using Verilog-HDL language in Xilinx 13.2ISE simulator and implements on Spartan 3E board.

Keywords- Modified Booth Encoding Multiplier, CSA, CLA, signed-unsigned numbers.
Publication Details
Unique Identification Number - IJEDR1404046
Page Number(s) - 3674-367
Pubished in - Volume 2 | Issue 4 | Dec 2014
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Manthan J. Trivedi,  Vimal H. Nayak,  Mohmmed G. Vayada,   "Analysis of High Speed Parallel Multiplier ", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 4, pp.3674-367, Dec 2014, Available at :http://www.ijedr.org/papers/IJEDR1404046.pdf
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