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Efficient VLSI Architecture for Xilinx Vertex E based FFT & IFFT Structure
Mamta Raj,  Prof.Sanket Choudhary,  Dr.Soni Changlani
Implementation of digital signal processing (DSP) algorithms in hardware, such as field VLSI, requires a large number of multipliers. Fast, low area multiply-adds have become critical in modern commercial and image DSP applications. A high speed fast fourier transform (FFT) and IFFT design by using 8-bit, 16-bit 32-bit and 64-bit algorithm is presented in this paper. My work focus is on two key ideas for improving FFT and IFFT algorithm performance: (1) develop new high performance efficient complex multiplier structure. (2) Parallel processing used in this design. In all algorithms are implemented Xilinx vertex 2 device family and simulated Modalism.
Keywords- FFT, Ripple Carry Adder, Carry Select Adder, Vedic Multiplier
Unique Identification Number - IJEDR1404075Page Number(s) - 3855-3860Pubished in - Volume 2 | Issue 4 | Dec 2014DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Mamta Raj,  Prof.Sanket Choudhary,  Dr.Soni Changlani,   "Efficient VLSI Architecture for Xilinx Vertex E based FFT & IFFT Structure "
, International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 4, pp.3855-3860, Dec 2014, Available at :http://www.ijedr.org/papers/IJEDR1404075.pdf