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Paper Details
Paper Title
Performance Analysis of Efficient Virtual Channel Router for NoC
Authors
  Omprakash Ghorse,  Uma Shankar Kurmi,  Dharmendra Dongardiye
Abstract
The requirements of on-chip communication in many systems are best served through the implementation of a new generation chip-wide network. The physical interconnections on-chip becomes a limiting issue for performance and energy consumption. The communication latency of network on chip is one of the important factors which directly impact on the performance of the system- on-chip. In this paper we introduce a new router architecture that can perform the virtual channel allocation and switch allocation in parallel to reduce the latency (critical path). Due to the parallel operation of these two stages the packet can be transfer in a reduced pipeline .The experimental result shows that router can operate at the maximum frequency and also reduction in the chip area.
Keywords- virtual channel, speculation
Publication Details
Unique Identification Number - IJEDR1502100Page Number(s) - 544-549Pubished in - Volume 3 | Issue 2 | May 2015DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Omprakash Ghorse,  Uma Shankar Kurmi,  Dharmendra Dongardiye,   "Performance Analysis of Efficient Virtual Channel Router for NoC", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 2, pp.544-549, May 2015, Available at :http://www.ijedr.org/papers/IJEDR1502100.pdf
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