Low Power High Speed Dynamic Latched Comparator

  Sakshi Parolia,  Shalini Singh

Two dynamic latched comparators with DC offset voltage compensation are presented. In this paper, the dynamic latched comparators demonstrates lower offset voltage and higher load drivability, with two different techniques one is on transistor resistance and other is on source degeneration. In these techniques different transistors are added to the input source, by which DC offset voltage and energy is improved. The proposed comparators are designed using 90 nm PTM technology and 1 V power supply voltage in cadence orCAD capture tool. It demonstrates less offset voltage and less sensitivity of delay to decreasing input voltage difference than the conventional double-tail latched type voltage sense amplifier at approximately the same area and power consumption.

Keywords- Dynamic comparator. Latched comparator. Voltage sense amplifier (SA). Low-offset low-power high-speed

Unique Identification Number - IJEDR1502139
Page Number(s) - 778-780
Pubished in - Volume 3 | Issue 2 | May 2015
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Sakshi Parolia,  Shalini Singh,   "Low Power High Speed Dynamic Latched Comparator", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 2, pp.778-780, May 2015, Available at :http://www.ijedr.org/papers/IJEDR1502139.pdf