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Paper Details
Paper Title
UART Design Using FIFO Ram and LCR Circuit with BIST Capability at Different Baud Rate
Authors
  Sandeep Singh Rawat,  Prof.Vishal Ramola
Abstract
The way integrated technology is growing becomes very difficult to apply circuit testing using Automatic TEST Equipment of complex circuit for this BIST (Built In Self test) is the solution of complex IC. Here we are applying BIST for UART which is considering as a low speed, low cost data exchange between computer and peripherals. Hence this paper shows implementation of UART with BIST capability using FIFO RAM, LCR at different baud rate, which solve the complex circuit testing with different baud rate it speed up the data handling capabilities of UART.
Keywords-
Publication Details
Unique Identification Number - IJEDR1503030Page Number(s) - Pubished in - Volume 3 | Issue 3 | July 2015DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Sandeep Singh Rawat,  Prof.Vishal Ramola,   "UART Design Using FIFO Ram and LCR Circuit with BIST Capability at Different Baud Rate", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 3, pp., July 2015, Available at :http://www.ijedr.org/papers/IJEDR1503030.pdf
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