Reduction of Leakage Power in CMOS circuits (Gates) using Variable Body Biasing with sleep insertion Technique

  Sunita Yadav,  Vishal Ramola

Leakage Power is the major problem in digital circuits. There are various techniques to reduce the leakage power technique. One technique discussed in this paper. We propose a technique called Variable body biasing for designing logic gates which significantly cuts down the leakage current without increasing the dynamic power dissipation, sleep insertion technique is also added along with variable body biasing technique so that there is no loss of state as in sleep stack technique. This thesis proposed a technique that reduces both power dissipation and glitches. This technique is based on two methods first is variable body biasing and the other is sleep insertion technique. Pass transistor is also added in the circuitry in order to eliminate glitches if any. The existing leakage reduction techniques like sleepy keeper and stack technique are having drawbacks like increased area and delay. Other delay elements that are used for reduction in glitches takes larger area when compared with pass transistor. This new proposed approach eliminates leakage power along with glitches keeping in mind all the drawbacks of all the earlier techniques. All the performance has been investigated using 90nm Technology at 1 voltage and evaluated by the comparison of the simulation result obtain from TSPICE.

Keywords- VBBT, Delay, leakage power, sleep insertion technique

Unique Identification Number - IJEDR1503056
Page Number(s) -
Pubished in - Volume 3 | Issue 3 | August 2015
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Sunita Yadav,  Vishal Ramola,   "Reduction of Leakage Power in CMOS circuits (Gates) using Variable Body Biasing with sleep insertion Technique", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 3, pp., August 2015, Available at :http://www.ijedr.org/papers/IJEDR1503056.pdf