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Paper Details
Paper Title
Reduction of Leakage Power in D-Flip Flop using LC nMOS Technique
Authors
  Abhishek Verma,  Vishal Ramola
Abstract
In CMOS circuits, Leakage Power dissipation is the major problem in front of the designers. There are various techniques introduced in the past decade to reduce the leakage power technique. One technique discussed in this paper. We propose a technique called LCnMOS for designing Full Adder which significantly reduce down the leakage current without increasing the switching power dissipation. LCnMOS, a technique to tackle the leakage problem in all digital circuits, uses single additional leakage control transistor LCT, driven by the output from the pull up and pull down networks, which is placed in a path from pull down network to ground. This LCT provides the additional resistance thereby reducing the leakage current in the path from supply to ground. All the performance has been investigated using 90nm and 180nm Technology at 1 voltage as power supply and evaluated by the comparison of the simulation result obtain from TSPICE.
Keywords- Leakage control Transistor nMOS, Delay, leakage power, LECTOR Technique, D- Flip Flop
Publication Details
Unique Identification Number - IJEDR1503071Page Number(s) - 1-7Pubished in - Volume 3 | Issue 3 | September 2015DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Abhishek Verma,  Vishal Ramola,   "Reduction of Leakage Power in D-Flip Flop using LC nMOS Technique", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 3, pp.1-7, September 2015, Available at :http://www.ijedr.org/papers/IJEDR1503071.pdf
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