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Survey on Implementation of IEEE754 Floating Point Number Division using Vedic Techniques
Rajani M,  S Sridevi
Abstract-Usually the processor arithmetic unit processes arithmetic operations, in that divider design is more critical as it consumes more area and power compared to other arithmetic operations.Efficient and compact Divider design has always been a challenging task. IEEE 754 floating point representations are considered as a computer storage format.This paper presents different Vedic division techniques which can be implemented in IEEE 754 floating point division format and also to study and compare the effect of various critical parameters in terms of power consumption and area utilization against conventional approaches.Vedic methods proven to be encouraging since this allows an easy and efficient way of computing various arithmetic computations.
Keywords- IEEE 754, Vedic division.
Unique Identification Number - IJEDR1503080Page Number(s) - Pubished in - Volume 3 | Issue 3 | 28 August 2015DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Rajani M,  S Sridevi,   "Survey on Implementation of IEEE754 Floating Point Number Division using Vedic Techniques"
, International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 3, pp., 28 August 2015, Available at :http://www.ijedr.org/papers/IJEDR1503080.pdf