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Paper Details
Paper Title
Design and Analysis of IO Blocks for 1024*16 CM8 SRAM
Authors
Md Tarique Ali, Kamil Hasan
Abstract
SRAM design is very crucial since it takes a large fraction of total power and die area in high-performance processors. The performance of embedded memory and its peripheral circuits can adversely affect the speed and power of the overall system. This paper explores the design of SRAM focusing on optimizing delay, reducing power and layout area. The key to low power operation of the design is self-timed architecture, multi stage decoding and full custom approach. A 1024x16 SRAM is designed at UMC 180 nm technology.
Keywords- Low power SRAM, Self-timed, Bit-line Fractioning, Multi-Stage decoding
Publication Details
Unique Identification Number - IJEDR1503090Page Number(s) - 1-4Pubished in - Volume 3 | Issue 3 | 25 September 2015DOI (Digital Object Identifier) - Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Md Tarique Ali, Kamil Hasan, "Design and Analysis of IO Blocks for 1024*16 CM8 SRAM", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 3, pp.1-4, 25 September 2015, Available at :http://www.ijedr.org/papers/IJEDR1503090.pdf
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