Synthesis & Simulation Model of Parallel Lift Controller Using Verilog

  Mohd Sabir Siddiqui,  Kamil Hasan

Machines are made to reduce human efforts and to save one’s time. The machines are elegantly built to suit the formal surroundings. Thus machines were made according to the human need. The high growth of the semiconductor industry over the past two decades has put Very Large Scale Integration in demand all over the world. The basics of digital logic theory and techniques are easily understood by the design based on VLSI technology. These are the core fundamentals of the fast, high-speed complex digital circuits. As day to day the technology is gradually improving. So obviously the designs have to be made simpler for enjoying the benefits. To do that, a Three-Lift Controller is modeled. In the proposed design a VERILOG RTL code is developed to control the lift moment based on the request it will get. For that a finite state machine is developed to know from which state to state the controller is changing based on the requests from the end user. Lift is also called as Elevator or car. The design is based on the synchronous input which should be operating with a fixed sort of frequency. Finally the RTL is verified and implemented in Precision Synthesis Tool. In this work, the real-time three-lift controller will be modeled with Verilog HDL code using Finite-State machine (FSM) model to achieve the logic in optimized way.

Keywords- FSM, Controller, Elevator control

Unique Identification Number - IJEDR1503094
Page Number(s) - 1-5
Pubished in - Volume 3 | Issue 3 | September 2015
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Mohd Sabir Siddiqui,  Kamil Hasan,   "Synthesis & Simulation Model of Parallel Lift Controller Using Verilog", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 3, pp.1-5, September 2015, Available at :http://www.ijedr.org/papers/IJEDR1503094.pdf