Design of Area-Delay-Power Efficient Carry Select Adder Using Cadence Tool

  G Venkatrao,  B.Jugal Kishore

In this paper the logic operations involved in binary to excess-1 converter (BEC) based CSLA and conventional carry select adder (CSLA) are analyzed to identify redundant logic operations. We eliminate all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation based CSLA. In the proposed technique, the carry select (CS) operation is scheduled before the calculation of final sum as output, which is different from the conventional approach. Bit patterns of two expected carry words cin (as 0 and 1) and fixed cin bits are used for logic optimization of CS and generation units. The proposed CSLA design involves less area, delay and power than conventional and BEC based CSLA. Due to the less carry-output delay the proposed CSLA design is efficient for analysis of square root (SQRT) CSLA.

Keywords- Adder, CSLA, SQRT-CSLA Delay, Low-power design

Unique Identification Number - IJEDR1503116
Page Number(s) - 1-6
Pubished in - Volume 3 | Issue 3 | September 2015
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  G Venkatrao,  B.Jugal Kishore,   "Design of Area-Delay-Power Efficient Carry Select Adder Using Cadence Tool", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 3, pp.1-6, September 2015, Available at :http://www.ijedr.org/papers/IJEDR1503116.pdf