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INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH
(International Peer Reviewed,Refereed, Indexed, Citation Open Access Journal)
ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Designing of efficient fpga pipelined architecture using spiht algorithm
Authors
  Vasundhara Hingal,  Prof. Pankaj Hedaoo,   Prof. Rahul Navkhare

Abstract
In this paper we present an efficient implementation of image compression of images through `Set Partitioning in Hierarchical Trees. (SPIHT) algorithm using FPGA. Routine SPIHT is reconfigurable logic. Traditionally computations requiring the high performance of a custom hardware implementation involved the development and fabrication of an Application Specific Integrated Circuit (ASIC). Development of an ASIC requires several steps. The circuit must be designed and then fabricated. SPIHT is a wavelet-based image compression coder. SPIHT is an algorithm which basically converts the image into its wavelet transform and then transmits the information in string of embedded coefficient. SPIHT is the method of coding and decoding the wavelet transformation of an image. By coding and transmitting information about the discrete wavelet coefficient, it is possible for a decoder to perform an inverse transformation on the wavelet and reconstruct the original image. The spiht algorithm can be applied to both grey scales as well as on color images. In this paper, the error resilience and compression speed are improved. The spiht coder is a highly improved version of L-Z algorithm and is an impactful image compression algorithm that produces an embedded bit stream from which the best reconstructed images can be extracted at various bit rates in the sense of mean square error. Some of the best results from SPIHT algorithm-PSNR values for given compression ratios for wide variety of images. Hence, it has become the benchmark state of algorithm for image compression.

Keywords- Image Compression, Spiht Encoding, Decoding, Spiht algorithm, decompression Images,LIS, LSP
Publication Details
Unique Identification Number - IJEDR1504016
Page Number(s) - 1-9
Pubished in - Volume 3 | Issue 4 | October 2015
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Vasundhara Hingal,  Prof. Pankaj Hedaoo,   Prof. Rahul Navkhare,   "Designing of efficient fpga pipelined architecture using spiht algorithm", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 4, pp.1-9, October 2015, Available at :http://www.ijedr.org/papers/IJEDR1504016.pdf
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