This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License
|
||||||||
|
Paper Details
Paper Title
Modelling of PLL based Frequency Multiplier System using VHDL - AMS – A Hardware Descriptive Language
Authors
Meet Poladia, Dheeraj Pandey
Abstract
This paper provides an overview of the VHDLAMS hardware description language for analog and mixed-signal applications like the phase locked loop system which is designed by describing the major elements or components of the system with the help of this hardware descriptive language and illustrating it using Hamster which is a simulation software for VHDL and Verilog Descriptive Language.
Keywords- PLL, VHDL – AMS, Verilog AMS, analog simulations, mixed signal simulations.
Publication Details
Unique Identification Number - IJEDR1504019Page Number(s) - 1-5Pubished in - Volume 3 | Issue 4 | October 2015DOI (Digital Object Identifier) - Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Meet Poladia, Dheeraj Pandey, "Modelling of PLL based Frequency Multiplier System using VHDL - AMS – A Hardware Descriptive Language", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 4, pp.1-5, October 2015, Available at :http://www.ijedr.org/papers/IJEDR1504019.pdf
Article Preview
|
|
||||||
|
|
||||||||
