Implementing Low Power and Efficient Image Encryption System Based On 128-Bit AES Algorithm On FPGA

  Shubhendu Kumar Mandloi,  Mukti Awad

In this paper, the proposed 128bits AES Scheme provides high secure and less area and presents optimized mix column architecture to get less area and delay than the presented mix column. In select a highly secured symmetric key encryption algorithm Advanced Encryption Standard, in order to increase the speed and throughput using pipeline technique in four stages, control unit based on logic gates, in optimal design of multiplier blocks in mixcolumn phase and simultaneous production keys and rounds. In the existing architecture, we are used complex mix-column in masked AES architecture. It consists of 8 multipliers and 11 adders. It consumes more area and power. In the proposed architecture, a novel mix column is introduced to reduce the area and power than the existing method. The proposed mix-column consists of only 12 adders and 4 X time circuit. Instead of normal multiple in the Mix Columns, we are using X time unit to reduce the circuit complexity. The 128 bits AES Scheme is used for ATM Net banking, Satellite Communication, Military applications.

Keywords- Encryption standard (AES), pipelining, signal gating, image encryption, decryption, etc.

Unique Identification Number - IJEDR1504092
Page Number(s) - 555-560
Pubished in - Volume 3 | Issue 4 | December 2015
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Shubhendu Kumar Mandloi,  Mukti Awad,   "Implementing Low Power and Efficient Image Encryption System Based On 128-Bit AES Algorithm On FPGA", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 4, pp.555-560, December 2015, Available at :http://www.ijedr.org/papers/IJEDR1504092.pdf