Design of High performance and Low Power 8T Full Adder Cell Using Double Gate MOSFET at 45nm Technology

  Shalini,  Mrs. Deepti Malhotra

Design of complex arithmetic logic circuits considering active power and delay is an important and challenging task in deep submicron circuits. Double gate transistor circuit consider as a promising candidate for low power application domain as well as used in Radio Frequency (RF) devices. In this paper we designed full adder with the help of double gate transistor, the used parameters value has been varied significantly thus improving the performance of full adder. Power Gating is one of the most used circuit techniques to reduce the leakage current in idle circuit. In this paper different parameters are analysed on Power Gating Technique. Power Gating technique achieves 93% reduction of leakage current, active power is reduced by 65% and delay is reduced by 24% as compared with conventional double gate full adder. Simulation results of double gate full adder have been performed on cadence virtuoso with 45nm technology.

Keywords- Power Gating, Double-gate MOSFETs, full adder, Power, Delay.

Unique Identification Number - IJEDR1504129
Page Number(s) - 744-749
Pubished in - Volume 3 | Issue 4 | December 2015
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Shalini,  Mrs. Deepti Malhotra,   "Design of High performance and Low Power 8T Full Adder Cell Using Double Gate MOSFET at 45nm Technology", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 4, pp.744-749, December 2015, Available at :http://www.ijedr.org/papers/IJEDR1504129.pdf