This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License
|
||||||||
|
Paper Details
Paper Title
Modified128 bit CSLA For Effective Area and Speed
Authors
Shaik Bademia Babu, Sada.Ravindar
Abstract
In the design of Integrated circuits, area occupancy plays a vital role because of increasing necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing Processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is to reduce the area of CSLA based on the efficient gate-level modification. In this paper 128 bits Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA BEC; the Modified SQRT CSLA BEC has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA BEC provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture.Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4.Then the implementation is done in Virtex5 FPGA Kit.
Keywords- Regular Linear CSLA,Modified Linear CSLA,Square-root CSLA (SQRT CSLA),dual Ripple Carry Adder (RCA)
Publication Details
Unique Identification Number - IJEDR1602027Page Number(s) - 165-169Pubished in - Volume 4 | Issue 2 | April 2016DOI (Digital Object Identifier) - plot no.36Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Shaik Bademia Babu, Sada.Ravindar, "Modified128 bit CSLA For Effective Area and Speed", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.4, Issue 2, pp.165-169, April 2016, Available at :http://www.ijedr.org/papers/IJEDR1602027.pdf
Article Preview
|
|
||||||
|
|
||||||||
