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Paper Details
Paper Title
A Review of Design of Efficient ALU
Authors
Gurneet Kaur Gill, Paramveer Singh Gill
Abstract
Most of the recent scientific operations take DSP operations into consideration. Arithmetic and logical unit is the main part of a digital processor. The fastness of a processor is controlled mainly by the multiplication unit ,as arithmetic and logic units are engaged for diverse areas ,places at which handling some of signals become necessary. Multipliers play extremely vital role in ALU design. Although some different algorithms of multiplication are in utilization, the implementation of multiplication units build on Vedic mathematics have not get much recognition. It includes the incomplete products headed by additive evaluation, in a one step. The design and implementation lessens the complication of the prototype of multiplier.
Keywords- Architecture,Vedic Multiplier,Multiplication
Publication Details
Unique Identification Number - IJEDR1602065Page Number(s) - 366-368Pubished in - Volume 4 | Issue 2 | April 2016DOI (Digital Object Identifier) - Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Gurneet Kaur Gill, Paramveer Singh Gill, "A Review of Design of Efficient ALU", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.4, Issue 2, pp.366-368, April 2016, Available at :http://www.ijedr.org/papers/IJEDR1602065.pdf
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