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Paper Details
Paper Title
Efficient Design of Area Delay Power Carry Select Adder
Authors
Chandra Bihari Goyal, Sharath GM, Ansuman Mishra
Abstract
Adders are one of the most important components in the digital logic used in every Integrated Circuit. To speed up the binary operations in an IC, high performance adders should be used. The requirements of an adder consists of low power consumption, small chip area and extremely fast. Carry Select Adder (CSLA) and Carry Look Ahead Adder (CLA) belongs to the class of high performance adders. The conventional Ripple Carry Adder (RCA) based CSLA and Binary to Excess 1 (BEC) based CSLA involves higher delay. In this paper, we proposed a delay and power efficient CLA based CSLA to overcome the disadvantages with conventional CSLA’s.
Keywords- Carry Select Adder, Carry Look Ahead Adder, Ripple Carry Adder etc.
Publication Details
Unique Identification Number - IJEDR1602067Page Number(s) - 374-377Pubished in - Volume 4 | Issue 2 | April 2016DOI (Digital Object Identifier) - Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Chandra Bihari Goyal, Sharath GM, Ansuman Mishra, "Efficient Design of Area Delay Power Carry Select Adder", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.4, Issue 2, pp.374-377, April 2016, Available at :http://www.ijedr.org/papers/IJEDR1602067.pdf
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