Design of Energy Efficient Low Power Adder using Multi-mode Addition

  P.Sangeetha,  M.Thiruppathi

Adders are usually designed for the worst case where their carry propagates through across the entire bits, those cases rarely occur at real operation. This work takes advantage of the infrequent worst-case occurrences by designing adders for the average case. Such design indicates that computation errors may occur. Those are being modified by implementing multi-mode addition with the help of a dedicated control circuit. A power-delay-energy model is presented, allowing to find the optimum design point. We demonstration for that situations where the system's critical paths are prescribed by the adders, the system's operation voltage can be scaled, without harming the clock cycle and with extremely small performance degradation. The multi-mode adder has been integrated in a 32-bit pipelined MIPS processor, proving the correctness of such design methodology.

Keywords- low power design, multi-mode adders, voltage scaling

Unique Identification Number - IJEDR1604064
Page Number(s) - 420-425
Pubished in - Volume 4 | Issue 4 | November 2016
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  P.Sangeetha,  M.Thiruppathi,   "Design of Energy Efficient Low Power Adder using Multi-mode Addition", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.4, Issue 4, pp.420-425, November 2016, Available at :http://www.ijedr.org/papers/IJEDR1604064.pdf