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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Details
Paper Title
Design of dexterous VLSI architecture of FFT using verilog
Authors
  P.Thirunavukku arasi,  P.S.Stellabai

Abstract
— Fast Fourier Transform (FFT) having a considerable impact on the performance of communication system has been a hot topic of research for many years. Fixed point numbers are most widely involved in FFT computation, in which the accuracy is one of the most important backlogs. Thus the floating point operation was included in butterfly unit. However, FP butterfly architecture has the main disadvantage is slow as compared with the fixed point computation. In this paper, the floating point fused dot product unit is used for latency reduction. Efficient Radix8 butterfly unit with FDPA was proposed. This butterfly unit performs faster than the conventional butterfly. Finally, the performance analysis of various Radix architectures such as Radix2, Radix4 and Radix8 are shown.Radix8 requires less number of adders and multipliers when compared to the other lower order radices. Thus the Radix8 architecture was chosen, in which the FDPA algorithm was implemented. Hence the speed of FFT computation with FP multiplier can be enhanced.

Keywords- Fused Dot Product Add (FDPA), Fast Fourier Transform (FFT), Floating Point multiplier (FP).
Publication Details
Unique Identification Number - IJEDR1702076
Page Number(s) - 444-447
Pubished in - Volume 5 | Issue 2 | April 2017
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  P.Thirunavukku arasi,  P.S.Stellabai,   "Design of dexterous VLSI architecture of FFT using verilog", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 2, pp.444-447, April 2017, Available at :http://www.ijedr.org/papers/IJEDR1702076.pdf
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