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Design and Simulation of Low Power and Area Efficient 16x16 bit Hybrid Multiplier
Juili Borkar,  Dr. U.M.Gokhale
Multiplication or repeated addition is the basic arithmetic operation used in both Mathematics and Science. Multiplier is one of the important hardware elements in most of the digital processing system such as digital signal processors, FIR filters and ALU in microprocessors etc. The two important parameters of a multiplier design are its area and speed that are inversely proportional.
The main key problem in design of VLSI circuits are larger area utilization, high power consumption and delay which affect the speed of computation and also result in power dissipation. In general, consideration, speed, and power are the essential factor in VLSI design. For solving this problem, a new architecture has been proposed. In proposed system, two high speed multipliers are used such as; modified booth multiplier and Wallace tree multiplier are hybridized with modified carry select adder (CSLA) which delivers high speed computation with low power consumption. Modified booth multiplier is proposed to reduce the partial product where as a Wallace tree multiplier is used for fast addition of partial products and CSLA used for final accumulation. This paper presents design of 16x16 Hybrid Multiplier based on modified booth and Wallace tree architecture.
Keywords- Modified booth algorithm, Wallace tree structure, Carry select adder
Unique Identification Number - IJEDR1702138Page Number(s) - 831-838Pubished in - Volume 5 | Issue 2 | May 2017DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Juili Borkar,  Dr. U.M.Gokhale,   "Design and Simulation of Low Power and Area Efficient 16x16 bit Hybrid Multiplier"
, International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 2, pp.831-838, May 2017, Available at :http://www.ijedr.org/papers/IJEDR1702138.pdf