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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Design and Implementation of FPGA based Logic in Memory Multiprocessor Architecture for Multi-Valued Data Transfer Schemes
Authors
  Shaik Nazeer,  N. Samba Murthy,  Dr. M. Kamaraju

Abstract
Intensive computational architecture is to take on huge parallelism, with a lot of concurrent tasks to execute simultaneously. This approach has many advantages, such as the reduced design time given by circuit replication and an increasing in computational speed without the need of higher frequency. Communication bottle neck between memory and logic module is one of the most serious problems in VLSI systems, so it is an important proof for bottle neck in data exchange between memory and logic module. To solve this, a new logic-in-memory VLSI architecture based on multi-valued data transfer is proposed to solve the communication bottleneck between memory and logic modules. Logic-in-Memory (LIM) architecture mixes logic and memory in the same device, removing the bottleneck of other existing parallel. By this we achieve power optimization under a time/area constraint, soft computing is investigated towards optimization of low power VLSI architecture design. So, this logic-in-memory architecture to solve the data transfer bottlenecks.

Keywords- LIM, soft computing, VLSI, Logic module.
Publication Details
Unique Identification Number - IJEDR1702154
Page Number(s) - 922-930
Pubished in - Volume 5 | Issue 2 | May 2017
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Shaik Nazeer,  N. Samba Murthy,  Dr. M. Kamaraju,   "Design and Implementation of FPGA based Logic in Memory Multiprocessor Architecture for Multi-Valued Data Transfer Schemes", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 2, pp.922-930, May 2017, Available at :http://www.ijedr.org/papers/IJEDR1702154.pdf
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