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Comparison of Conventional low Power Flip Flops with Pulse Triggered Generation using Signal Feed through technique.
Inder Singh,  VinayKumar
The objective to design and compare a low-power flip-flop (FF) design presenting an Explicit type pulse-triggered framework . Pulse triggered method use used for clock to resolves lengthy discharging path issue in conventional explicit type pulse-triggered FF (P-FF) design and achieves better rate and energy efficiency. a novel power effective pulse triggered flip flop design with lowest no. of transistors is suggested. Various publish structure simulator outcomes based on Mentor Eldo Simmulator CMOS 180-nm technology .
Keywords- Flip flop, low power, pulse triggered, signal feed through
Unique Identification Number - IJEDR1702201Page Number(s) - 1243-1248Pubished in - Volume 5 | Issue 2 | May 2017DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Inder Singh,  VinayKumar,   "Comparison of Conventional low Power Flip Flops with Pulse Triggered Generation using Signal Feed through technique."
, International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 2, pp.1243-1248, May 2017, Available at :http://www.ijedr.org/papers/IJEDR1702201.pdf