Performance analysis of Modified SRAM Memory Design using leakage power reduction

  Udaya Bhaskar.Pragada ,  J.S.S.Rama Raju,  Mahesh Gudivaka

The present world aims in designing low power devices due to the rampant usage of portable battery powered gadgets. The proposed static random access memory (SRAM) design furnishes an approach towards curtailing the hold power dissipation. The design uses a tail transistor which aids in limiting the short circuit power dissipation by disrupting the direct connection between supply voltage and ground. This tail transistor also brings down the subthreshold current by providing stacking effect, which subsequently reduces hold power dissipation. A supply voltage of 0.8V is used which makes it eligible for low power applications. The designed SRAM cell has single ended write and read operations and is simulated using TANNER EDA 45nm CMOS technology. The proposed SRAM cell has a low power consumptionwhich is much less as compared to the standard 6T SRAM cell.

Keywords- power consumption, hold power dissipation, SRAM, stacking effect, subthreshold current

Unique Identification Number - IJEDR1702284
Page Number(s) - 1814-1820
Pubished in - Volume 5 | Issue 2 | June 2017
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Udaya Bhaskar.Pragada ,  J.S.S.Rama Raju,  Mahesh Gudivaka,   "Performance analysis of Modified SRAM Memory Design using leakage power reduction", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 2, pp.1814-1820, June 2017, Available at :http://www.ijedr.org/papers/IJEDR1702284.pdf