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INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH
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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
High Performance and Low Power 8 bit 16T full adder using MTCMOS Technique
Authors
  Neeraj Singla,  Jasbir kaur

Abstract
The most fundamental operation of any processor is the addition. For any circuit there are two important parameters that comes into count is high speed and low power consumption. Hence the speed of various modules should be maximized to dominate overall performance. Depending upon these parameters various adders can be invented like Carry Look Ahead Adder(CLA),Carry Skip Adder(CSA) and Ripple Carry Adder (RCA). The main objective of this paper to provide solution of these parameters at very large scale integration such as 8 bit adder. The main objective of this paper is to provide new low power solution for Very Large Scale Integration (VLSI). One of the most effective technique is MTCMOS which utilizes high as well as low threshold voltage transistors. MTCMOS technique has very small power dissipation as compared to conventional technique and simulation is done using cadence virtuoso 180nm CMOS technology. This paper compares 8 bit 16T full adder using MTCMOS with the conventional full adder. MTCMOS circuit has very small power dissipation and high speed. Static power dissipation reduced to large extent.

Keywords- Keywords- RCA, 16T full adder, MTCMOS technique.
Publication Details
Unique Identification Number - IJEDR1702304
Page Number(s) - 1955-1961
Pubished in - Volume 5 | Issue 2 | June 2017
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Neeraj Singla,  Jasbir kaur,   "High Performance and Low Power 8 bit 16T full adder using MTCMOS Technique", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 2, pp.1955-1961, June 2017, Available at :http://www.ijedr.org/papers/IJEDR1702304.pdf
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