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INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH
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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Simulation of SHA-3 Algorithm (KECCAK) With Area Efficient Module
Authors
  Priya Kotewar,  Prof. R.N.Mandavgane,  Prof.D.M.Khatri

Abstract
Abstract: SHA-3 is widely used in security protocols and applications such as message authentication in wireless senor nodes. Efficient implementation of SHA-3 is desired to achieve speed and power performance. In this paper, design, simulation and implementation of SHA-3 Keccak algorithm on Xilinx ISE software is presented. The design was coded in VHDL and implemented on Vertex 6 FPGA.The objective of the work was to achieve minimum gate count or area so as to increase speed and decrease power dissipation. Results clearly indicate that the presented design achieve less area and high speed.

Keywords- SHA-3, Keccak-512.
Publication Details
Unique Identification Number - IJEDR1702323
Page Number(s) - 2075-2079
Pubished in - Volume 5 | Issue 2 | June 2017
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Priya Kotewar,  Prof. R.N.Mandavgane,  Prof.D.M.Khatri,   "Simulation of SHA-3 Algorithm (KECCAK) With Area Efficient Module", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 2, pp.2075-2079, June 2017, Available at :http://www.ijedr.org/papers/IJEDR1702323.pdf
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