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INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH
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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Scalable Packet Classification on FPGA
Authors
  Deepak K. Thakkar,  Dr. B. S. Agarkar

Abstract
Abstract—Packet classification is used in networking for sorting out packets into flows by comparing packet headers with rules in classifier. A flow is used to decide what action is to be taken on incoming packet. Now a days it is great challenge to develop scalable solutions for advanced packet classification which is having higher performance, supports large rule sets as well as more packet header fields. This paper provides software as well as hardware implementation of HiCuts and HyperCuts algorithms by using Xilinx Vivado2016.1 software tool and Genesys 2 Kintex-7 FPGA development board with Xilinx Kintex-7 FPGA device X7K325T-2FG900C. Thus implementation results shows that HyperCuts algorithm is superior than HiCuts with respect to many parameters such as depth of decision tree, execution time and memory requirements with the different number of rules. The depth of decision tree is 1 and execution time for Hypercuts algorithms is 0.779ns for all cases which is less than that of HiCuts algorithms. Also in many cases the memory requirements of HyperCuts is less than HiCuts algorithm. To test these algorithms we consider ACL rule set.

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Publication Details
Unique Identification Number - IJEDR1703077
Page Number(s) - 521-528
Pubished in - Volume 5 | Issue 3 | August 2017
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Deepak K. Thakkar,  Dr. B. S. Agarkar ,   "Scalable Packet Classification on FPGA", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 3, pp.521-528, August 2017, Available at :http://www.ijedr.org/papers/IJEDR1703077.pdf
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