Novel Low Power and High speed CMOS based XOR/XNORs using Systematic Cell Design Methodology

  Ashok Yadav,  Dr. Manish Jain

The XOR and XNOR gates are the essential blocks of various digital arithmetic and logical units such as digital adder, digital parity generator/checker and digital comparator. Many circuit topologies have been proposed till now of full adder and XOR/XNOR gate design that can be categorised in two categories. First category offers full swing output and second category offers partial swing output. The Systematic Cell Design Methodology is partial swing based logic design method which offers less delay and low power consumption at weak logic ‘0’ and logic ‘1’ generation at output. The proposed 18T design offers least delay and power dissipation as compared with existing design. The existing design TG16T, TGM16T, TGM18T, TF, Hybrid and LPHA-FA offers 6%, 6%, 22%, 28%, 61% and 111% higher average propagation delay than proposed 18T XOR/XNOR design, while offers 16%, 23%, 19%, 9%, 2%, 33% higher average power dissipation than proposed 18T XOR/XNOR design. In this work results are simulated at 1.2Volt and 130nm technology.

Keywords- Hybrid CMOS logic, XOR/XNOR gate, partial swing logic, full swing logic.

Unique Identification Number - IJEDR1703143
Page Number(s) - 1018-1024
Pubished in - Volume 5 | Issue 3 | September 2017
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Ashok Yadav,  Dr. Manish Jain,   "Novel Low Power and High speed CMOS based XOR/XNORs using Systematic Cell Design Methodology", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 3, pp.1018-1024, September 2017, Available at :http://www.ijedr.org/papers/IJEDR1703143.pdf