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Paper Details
Paper Title
LFSR Design using Low Transition for BIST
Authors
R.Sree santhi
Abstract
This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within random test pattern and between consecutive patterns. In other words, transitions are reduced in two dimensions, i.e. between consecutive patterns (fed to a combinational circuit) and consecutive bits (sent to a scan chain). LT-LFSR is independent of circuit under test and flexible to be used for both BIST and scan-based BIST architectures
Keywords- low power,BIST
Publication Details
Unique Identification Number - IJEDR1801064Page Number(s) - 378-382Pubished in - Volume 6 | Issue 1 | January 2018DOI (Digital Object Identifier) - Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
R.Sree santhi, "LFSR Design using Low Transition for BIST", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.6, Issue 1, pp.378-382, January 2018, Available at :http://www.ijedr.org/papers/IJEDR1801064.pdf
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