Real time Image Processing and hardware implementation on FPGA using VHDL

  Aayushi Jain,  Sunil Shah

We present in this work an image component labeler-and feature extraction module that can operate in real-time. Connected component labeling may be used as a relatively fast method to detect and extract features from images containing relatively homogeneous pixel values in a gray scale setting. This labeler is suitable for smart cameras and Field Programmable Gate Arrays (FPGA). We show in our work how complex gray value features of image components can be calculated in parallel with label assignment without first resolving complex chains of merged labels. By isolating region in “blobs” of accepted regions. The blobs may have their data extracted and further analyzed to aid in verification of which extracted blob matches features sought by the user. In this paper we present a prototype application that implements connected component labeling .The labeler and a simple counter of number of image components are implemented on a Xilinx Virtex II Pro. We report device usage, maximum frequency and power dissipation.

Keywords- IMAGE PROCESSING , FPGA , VHDL

Unique Identification Number - IJEDR1801133
Page Number(s) - 771-780
Pubished in - Volume 6 | Issue 1 | March 2018
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Aayushi Jain,  Sunil Shah,   "Real time Image Processing and hardware implementation on FPGA using VHDL", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.6, Issue 1, pp.771-780, March 2018, Available at :http://www.ijedr.org/papers/IJEDR1801133.pdf