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Paper Details
Paper Title
Lightweight Hardware Architectures for PRESENT Cipher in FPGA
Authors
  Suresh.H,  R Vignesh Chandrasekhar
Abstract
Lightweight symmetric ciphers have gained interest in constrained computing due to the increasing demand for security services as in the Internet of Things. This paper discusses the hardware implementations of PRESENT, a standardized lightweight cipher designed to overcome part of the security issues in extremely constrained conditions. The most representative realizations of this cipher are reviewed and two novel designs are presented. Using the same implementation conditions, the two new proposals and three state-of-the-art designs are evaluated and compared using area, performance, energy, and efficiency as metrics. In particular, this design results to be adequate in regards to energy-per-bit and throughput-per-slice.
Keywords- cipher, IoT , PRESENT
Publication Details
Unique Identification Number - IJEDR1801158Page Number(s) - 914-924Pubished in - Volume 6 | Issue 1 | March 2018DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Suresh.H,  R Vignesh Chandrasekhar,   "Lightweight Hardware Architectures for PRESENT Cipher in FPGA", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.6, Issue 1, pp.914-924, March 2018, Available at :http://www.ijedr.org/papers/IJEDR1801158.pdf
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