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Paper Title
Optimization Of A Four Bit Digital Multiplier Design Using Mosfet And Finfet Technology
  Farhana Hamid Bhat,  Er Arti Goel

In this paper, a low power ultra-high speed multiplier is proposed by utilizing voltage scaling system for FinFET dual mode technique. A Multiplier design is implemented in MOSFET 32nm and also in FinFET 32nm, performance is compared on the basis of Average power Consumption and Delay. A variation of Number of fins versus Average power is also calculated. Simulation results are obtained using Synopsys HSPICE software, and they show that dual mode multiplier technique is low power. Delay is also improved when FinFETs are used in the Multiplier.

Keywords- Multiplier, Dual Mode, FinFET, 32nm
Publication Details
Unique Identification Number - IJEDR1802029
Page Number(s) - 160-164
Pubished in - Volume 6 | Issue 2 | April 2018
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Farhana Hamid Bhat,  Er Arti Goel,   "Optimization Of A Four Bit Digital Multiplier Design Using Mosfet And Finfet Technology", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.6, Issue 2, pp.160-164, April 2018, Available at :http://www.ijedr.org/papers/IJEDR1802029.pdf
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