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Paper Details
Paper Title
Review Paper on Vedic Multiplier by Using Different Methods
Authors
Manpreet kaur, Amandeep kaur
Abstract
In digital circuits multiplier has important role. These are the main important blocks in many applications like digital signal processing, microprocessor and microcomputers. The time that required to do calculation in multiplier is reduced by using vedic multipliers. Vedic Mathematics is the fastest and low power multiplier. Vedic Mathematics have sixteen sutras but “Urdhva Tiryagbhyam” is maily used .In this paper 16 bit Vedic multiplier is designed by using modified full adders which has used less number of slices and delay is reduced when compared to existing techniques of Vedic Multiplier. Simulation and synthesis are carried on XILINX ISE 14.4 software.
Keywords- Vedic Multiplier, Full Adder using Multiplexer, Ripple Carry Adder, VLSI.
Publication Details
Unique Identification Number - IJEDR1802103Page Number(s) - 574-577Pubished in - Volume 6 | Issue 2 | June 2018DOI (Digital Object Identifier) - Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Manpreet kaur, Amandeep kaur, "Review Paper on Vedic Multiplier by Using Different Methods", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.6, Issue 2, pp.574-577, June 2018, Available at :http://www.ijedr.org/papers/IJEDR1802103.pdf
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