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Paper Details
Paper Title
Power Analysis of Novel Glitch Resistant DET-FF
Authors
Dr. Sumitra Singar, Prof. N.K.Joshi, Prof. P. K. Ghosh
Abstract
This paper presents the design of novel low power glitch resistant DET-FF. The presented glitch resistant DET-FF reduces the delay and average power consumption and increases the speed of the device. To improve the results, the 1P-2N structure combined with the C-element structure. To reduce the area, the two 1P-2N structures are merged. The proposed novel glitch resistant DET-FF is implemented with 32 nm CMOS technology and simulated through the SPICE. The power supply voltage and system clock frequency of proposed novel glitch resistant DET-FF are fixed to 1V and 500 MHz respectively.
Keywords- Average power consumption; Clock networks; Dual edge triggered; Glitch resistant; Power delay product.
Publication Details
Unique Identification Number - IJEDR1901020Page Number(s) - 96-100Pubished in - Volume 7 | Issue 1 | January 2019DOI (Digital Object Identifier) - Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Dr. Sumitra Singar, Prof. N.K.Joshi, Prof. P. K. Ghosh, "Power Analysis of Novel Glitch Resistant DET-FF", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.7, Issue 1, pp.96-100, January 2019, Available at :http://www.ijedr.org/papers/IJEDR1901020.pdf
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