Low Cost Journal,International Peer Reviewed and Refereed Journals,Fast Paper Publication approved journal IJEDR(ISSN 2321-9939) apply for ugc care approved journal, UGC Approved Journal, ugc approved journal, ugc approved list of journal, ugc care journal, care journal, UGC-CARE list, New UGC-CARE Reference List, UGC CARE Journals, ugc care list of journal, ugc care list 2020, ugc care approved journal, ugc care list 2020, new ugc approved journal in 2020, Low cost research journal, Online international research journal, Peer-reviewed, and Refereed Journals, scholarly journals, impact factor 7.37 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool)
INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH
(International Peer Reviewed,Refereed, Indexed, Citation Open Access Journal)
ISSN: 2321-9939 | ESTD Year: 2013

Current Issue

Call For Papers
July 2022

Volume 10 | Issue 3
Last Date : 29 July 2022
Review Results: Within 12-20 Days

For Authors

Archives

Indexing Partner

Research Area

LICENSE

Paper Details
Paper Title
Performance Comparison of 1-bit Full Adders using 180 nm CMOS Technology
Authors
  Bhagyashree,  Shashidhara K.S,  Dr.Parameshwara M.C

Abstract
This paper discusses the performance comparison of various state-of-the-art 1-bit full adder (FA) cells. All these FA cells have been derived using static CMOS and its constituent logic styles such as pass transistor logic (PTL), transmission gate logic (TGL). The design of the state-of-the-art 1-bit FA cells is carried out using Cadences’ generic 180 nm based process design kit (GPDK). The performance of the FA cells is compared and analyzed in terms of design metrics (DMs) such as power, delay, power-delay-product (PDP), and area in terms of transistor count (TC). From the comparison results, for 1.8 V supply voltage and operating frequency 100 MHz, the average power consumption of Double-Pass Transistor Logic (DPL) based 1-bit FA is (143.1 µW) was found to be extremely low with moderately low delay (133.4 pS) and low PDP (19.08fJ). Further the FAs are analyzed in terms of DMs under variable load and power supply conditions.

Keywords- full adder, adder, low power, PDP, 180 nm GPDK.
Publication Details
Unique Identification Number - IJEDR1903016
Page Number(s) - 86-90
Pubished in - Volume 7 | Issue 3 | July 2019
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Bhagyashree,  Shashidhara K.S,  Dr.Parameshwara M.C,   "Performance Comparison of 1-bit Full Adders using 180 nm CMOS Technology", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.7, Issue 3, pp.86-90, July 2019, Available at :http://www.ijedr.org/papers/IJEDR1903016.pdf
Share This Article


Article Preview

ISSN Details




DOI Details



Providing A digital object identifier by DOI
How to get DOI?

For Reviewer /Referral (RMS)

Important Links

NEWS & Conference

Digital Library

Our Social Link

© Copyright 2022 IJEDR.ORG All rights reserved