Performance Comparison of 1-bit Full Adders using 180 nm CMOS Technology

  Bhagyashree,  Shashidhara K.S,  Dr.Parameshwara M.C

This paper discusses the performance comparison of various state-of-the-art 1-bit full adder (FA) cells. All these FA cells have been derived using static CMOS and its constituent logic styles such as pass transistor logic (PTL), transmission gate logic (TGL). The design of the state-of-the-art 1-bit FA cells is carried out using Cadences’ generic 180 nm based process design kit (GPDK). The performance of the FA cells is compared and analyzed in terms of design metrics (DMs) such as power, delay, power-delay-product (PDP), and area in terms of transistor count (TC). From the comparison results, for 1.8 V supply voltage and operating frequency 100 MHz, the average power consumption of Double-Pass Transistor Logic (DPL) based 1-bit FA is (143.1 µW) was found to be extremely low with moderately low delay (133.4 pS) and low PDP (19.08fJ). Further the FAs are analyzed in terms of DMs under variable load and power supply conditions.

Keywords- full adder, adder, low power, PDP, 180 nm GPDK.

Unique Identification Number - IJEDR1903016
Page Number(s) - 86-90
Pubished in - Volume 7 | Issue 3 | July 2019
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Bhagyashree,  Shashidhara K.S,  Dr.Parameshwara M.C,   "Performance Comparison of 1-bit Full Adders using 180 nm CMOS Technology", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.7, Issue 3, pp.86-90, July 2019, Available at :http://www.ijedr.org/papers/IJEDR1903016.pdf