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INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH
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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Investigation of Low Power Sample and Hold Circuit for Analog to Digital Converter
Authors
  Shivali

Abstract
Sample and hold circuit is an important part of an analog to digital converter. Being part of the ADC sample and hold is consuming high power. For low power consumption, various sample and hold circuits like Bootstrap Circuit, Low-Power Bootstrapped S/H Circuit without Multiplier Circuit & Boosted Driver Circuit are investigated for better performance and low power consumption at different frequency applications such as audio, Bluetooth and video frequencies. The effect of the low-power bootstrapped sample and hold (S/H) circuit without multiplier appears in the medium and high-frequency applications which reduce the power consumption without disturbing the signal-to-noise and distortion ratio (SNDR). All the introduced bootstrapped sample and hold (S/H) circuits were simulated using 90nm, 65nm & 45nm CMOS technology on LT Spice VIII. As a result, the planned low power bootstrapped sample and hold (S/H) circuit without multiplier save 78% to 93% for 90nm & 65nm while 84% to 94% for 45nm of the power consumption.

Keywords- ADC, Sample and Hold Circuit, Transmission Gate, Bootstrapped Circuit without Multiplier.
Publication Details
Unique Identification Number - IJEDR1904060
Page Number(s) - 341-347
Pubished in - Volume 7 | Issue 4 | October 2019
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Shivali,   "Investigation of Low Power Sample and Hold Circuit for Analog to Digital Converter", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.7, Issue 4, pp.341-347, October 2019, Available at :http://www.ijedr.org/papers/IJEDR1904060.pdf
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