Theoretical Study of Low Power Sample and Hold Circuit for Analog to Digital Converter

  shivali

In this paper, we can study the sample and hold circuit which consumes high power to being part of the ADC. For low power consumption, various sample and hold circuits like Bootstrap Circuit, Low-Power Bootstrapped S/H Circuit without Multiplier Circuit & Boosted Driver Circuit is used for better performance and low power consumption at different frequency applications such as audio, Bluetooth and video frequencies. The effect of the low-power bootstrapped sample and hold circuit without multiplier shows in the medium and high-frequency applications which may show the reduced power consumption without disturbing the signal-to-noise and distortion ratio (SNDR). All the used bootstrapped sample and hold circuits were simulating using 90nm, 65nm & 45nm CMOS technology on LT Spice VIII. We can try to investigate the low power bootstrapped sample and hold circuit without multiplier saves 78% to 93% for 90nm & 65nm while 84% to 94% for 45nm of the power consumption.

Keywords- Analog to Digital Converter, Sample and Hold Circuit, Transmission Gate, Bootstrapped Circuit without Multiplier.

Unique Identification Number - IJEDR1904062
Page Number(s) - 351-354
Pubished in - Volume 7 | Issue 4 | October 2019
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  shivali,   "Theoretical Study of Low Power Sample and Hold Circuit for Analog to Digital Converter", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.7, Issue 4, pp.351-354, October 2019, Available at :http://www.ijedr.org/papers/IJEDR1904062.pdf