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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Estimation Of Delay And Power Analysis Of Sense Amplifiers
  G. Poshamallu,  R. Radha,  J. Manasa,  R.Pruthvi

Sense amplifiers plays a necessary role in CMOS memories, it is mostly used to hurry the memory read operation in a cache memory both memory access time and overall memory power consumption affects the performance of sense amplifier by use of current mode than voltage mode signal transporting technique in this we use the low resistance current signal circuits to lower the impedance level and voltage swing on extended interconnect wire, the interruption for changed power supply voltages Vdd and for altered values of bit line capacitances are specified. Results of static power and total power consumption for unlike values of Vdd are simulated and analyzed.

Keywords- Sense Amplifier, Voltage SA, Current SA, Cross Coupled CMOS inverter SA, Latch type voltage SA, Hybrid mode SA, Delay, Power, Static Power.
Publication Details
Unique Identification Number - IJEDR2002012
Page Number(s) - 55-60
Pubished in - Volume 8 | Issue 2 | June 2020
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  G. Poshamallu,  R. Radha,  J. Manasa,  R.Pruthvi,   "Estimation Of Delay And Power Analysis Of Sense Amplifiers", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.8, Issue 2, pp.55-60, June 2020, Available at :http://www.ijedr.org/papers/IJEDR2002012.pdf
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