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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Design and Analysis of Radiation Hardened Latches for Nano-Scale CMOS
  Viraj Bhusari

Modern nanotechnology is advancing very fast and its operation is extensively analyzed and thus with the advancement at the level of nano-scale, the CMOS has become more sensitive to externally induced radiation which can cause induced errors called soft errors. So the tolerance to such errors is the strict requirement in the nano-scale industry. But traditional error tolerance method results in an increase in the power and area and at the same time a reduction in the performance of the circuit. This project deals with some new hardening circuits to improve performance and all other factors, these circuits are Schmitt-trigger based circuits and one circuit is used in cascode feedback loop. Schmitt–trigger based circuit gives the higher critical charge which is used as an analytical factor in the measurement of the degree of radiation hardening.

Keywords- Critical Charge; Schmitt-Trigger; Radiation Hardening
Publication Details
Unique Identification Number - IJEDR2002052
Page Number(s) - 309-313
Pubished in - Volume 8 | Issue 2 | April 2020
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Viraj Bhusari,   "Design and Analysis of Radiation Hardened Latches for Nano-Scale CMOS", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.8, Issue 2, pp.309-313, April 2020, Available at :http://www.ijedr.org/papers/IJEDR2002052.pdf
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