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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Optimization of power in different circuits using MTCMOS technique
  G.Raghu Nandan Reddy,  T.V. Ananthalakshmi

This paper enumerates low power, high speed designed circuits like 5T TSPC D-Flip Flop and 4T Schmitt trigger having less number of transistors. As the transistors used have small area and low power consumption, they can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors, etc. So the leakage current of these devices will increase significantly with the shrinking of semiconductor process technologies. The most straight forward and effective method for reducing standby leakage is power-gating. In this Multithreshold Voltage Based CMOS (MTCMOS) technique is used as a power gating method to optimize power and delay in the circuits.

Keywords- Power Gating, 5T D-flip flop, Schmitt trigger, Cadence tool
Publication Details
Unique Identification Number - IJEDR1402048
Page Number(s) - 1573-1582
Pubished in - Volume 2 | Issue 2 | June 2014
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  G.Raghu Nandan Reddy,  T.V. Ananthalakshmi,   "Optimization of power in different circuits using MTCMOS technique", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 2, pp.1573-1582, June 2014, Available at :http://www.ijedr.org/papers/IJEDR1402048.pdf
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