Hspice Simulation of D Latch and Double Edge Triggered Flip-Flop Using CNTFET

  Deepak V. Gohil,  Mr.Yogesh D. Parmar

The basic VLSI (Very Large Scale Integration) circuit element is Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Moore’s law states that, design performance improves by reduction in gate length. The gate length reduction is also known as scaling. The continuous scaling of the circuit design will cause issues related to electrical performance of the chip. The device fabrication creates major problems when the geometry reaches to nanometer region. For the same purpose, the researchers have found Carbon Nano-Tubes (CNT) as the new worthy candidate. The design of CNT defines its properties, either metallic conductor or semiconductor. The transistor made from CNT is referred as CNT Field Effect Transistor (CNTFET). In this paper, we have Simulate CNTFETs based D Latch and Double Edge triggered D Flip-Flop using Hspice. Section-1 gives brief introduction of MOSFETs and CNTFETs whereas section-2 describes the detailed properties of CNTFETs and section-3 gives details about CNTFET model. Section-4 describes the detailed description about D Latch and Double Edge Triggered D Flip-Flop with Simulation results. Section-5 summarizes the paper and shows future prospects of CNTFETs’ usage.

Keywords- CNTFET, MOSFET, Chirality, Graphene, I-V characteristic, VTC

Unique Identification Number - IJEDR1402229
Page Number(s) - 2734-2739
Pubished in - Volume 2 | Issue 2 | June 2014
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Deepak V. Gohil,  Mr.Yogesh D. Parmar,   "Hspice Simulation of D Latch and Double Edge Triggered Flip-Flop Using CNTFET", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 2, pp.2734-2739, June 2014, Available at :http://www.ijedr.org/papers/IJEDR1402229.pdf