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Optimization of time and area of a Cordic processor for Low power application
Savitha S,  Yogitha S
This paper presents an ideology of area and time efficient CORDIC algorithm that completely eliminates the scale-facto by the suitable selection of the order of approximation of Taylor series concept. The proposed CORDIC circuit attains the desired range of convergence and meets the accuracy requirement. An algorithm called Generalized micro-rotation selection technique has been implemented to redefine the elementary angles for reducing the number of CORDIC iterations. The proposed CORDIC processor provides the flexibility to change the number of iterations depending on the accuracy, area and latency requirements. The proposed Cordic processor was simulated in Modelsim6.1 and implemented on Xilinx Spartan XC2S500E device and Chipscope Pro in order to evaluate various parameters.
Keywords- coordinate rotation digital computer (CORDIC), cosine/sine, field-programmable gate array (FPGA).
Unique Identification Number - IJEDR1804085Page Number(s) - 471-476Pubished in - Volume 6 | Issue 4 | December 2018DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Savitha S,  Yogitha S,   "Optimization of time and area of a Cordic processor for Low power application"
, International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.6, Issue 4, pp.471-476, December 2018, Available at :http://www.ijedr.org/papers/IJEDR1804085.pdf