Low Cost Journal,International Peer Reviewed and Refereed Journals,Fast Paper Publication approved journal IJEDR(ISSN 2321-9939) apply for ugc care approved journal, UGC Approved Journal, ugc approved journal, ugc approved list of journal, ugc care journal, care journal, UGC-CARE list, New UGC-CARE Reference List, UGC CARE Journals, ugc care list of journal, ugc care list 2020, ugc care approved journal, ugc care list 2020, new ugc approved journal in 2020, Low cost research journal, Online international research journal, Peer-reviewed, and Refereed Journals, scholarly journals, impact factor 7.37 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool)
INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH
(International Peer Reviewed,Refereed, Indexed, Citation Open Access Journal)
ISSN: 2321-9939 | ESTD Year: 2013
Google Scholar Impact Factor- 7.37 (Year 2020)
Impact factor 7.37 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool), Scholarly open access , Peer-reviewed, and Refereed, Multidisciplinary, Indexing in all major database & Metadata, Citation Generator, Digital Object Identifier(DOI) journal.

Current Issue

Call For Papers
March 2020

Volume 8 | Issue 1
Last Date : 29 March 2020


Review Results: Within 02-04 Days
Paper Publish: Within 02-04 Days
Impact Factor : 7.37

For Authors

Archives

Indexing Partner

Research Area

LICENSE

Facts & Figures

Visitor Statistics


Paper Details
Paper Title
Adiabatic Logic Modelling using VHDL
Authors
  Shiwani Singh,  Sonam Rathore

Abstract
Adiabatic circuits are low power circuits which use reversible logic to conserve energy. Unlike traditional CMOS circuits, which dissipate energy during switching, adiabatic circuits reduce dissipation by never turning on a transistor when there is a voltage potential between the source and drain and never turning off a transistor when current is flowing through it. The verification of the functionality and the low energy traits of adiabatic logic techniques are generally performed using transient simulations at the transistor level. However, as the size and complexity of the adiabatic system increases, the amount of time required to design and simulate also increases. Moreover, due to the complexity of synchronizing the power-clock phases, debugging of errors becomes difficult too thus, increasing the overall verification time. Using the proposed approach, the functional errors can be detected and corrected at an early design stage so that when designing adiabatic circuits at the transistor level, the circuit performs correctly and the time for debugging the errors can substantially be reduced. The function is defined using a library containing the behavioral VHDL models of adiabatic domino XOR logic gate. Finally, this library is used to develop and verify the structural VHDL representation of a full adder, as a design example that demonstrates the practicality of the proposed approach. This paper proposes a VHSIC Hardware Descriptive Language (VHDL) based modelling approach for developing models representing single phase adiabatic logic designs.

Keywords- Adiabatic logic, domino, low power, XOR, adder and VHDL
Publication Details
Unique Identification Number - IJEDR2001024
Page Number(s) - 125-130
Pubished in - Volume 8 | Issue 1 | January 2020
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Shiwani Singh,  Sonam Rathore,   "Adiabatic Logic Modelling using VHDL", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.8, Issue 1, pp.125-130, January 2020, Available at :http://www.ijedr.org/papers/IJEDR2001024.pdf
Share This Article


Article Preview

ISSN Details




DOI Details



Providing A digital object identifier by DOI
How to get DOI?

For Reviewer /Referral (RMS)

Important Links

NEWS & Conference

Digital Library

Our Social Link

Open Access

This material is Open Knowledge
This material is Open Data
This material is Open Content
© Copyright 2020 IJEDR.ORG All rights reserved