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Paper Title
Adiabatic Logic Modelling using VHDL
  Shiwani Singh,  Sonam Rathore

Adiabatic circuits are low power circuits which use reversible logic to conserve energy. Unlike traditional CMOS circuits, which dissipate energy during switching, adiabatic circuits reduce dissipation by never turning on a transistor when there is a voltage potential between the source and drain and never turning off a transistor when current is flowing through it. The verification of the functionality and the low energy traits of adiabatic logic techniques are generally performed using transient simulations at the transistor level. However, as the size and complexity of the adiabatic system increases, the amount of time required to design and simulate also increases. Moreover, due to the complexity of synchronizing the power-clock phases, debugging of errors becomes difficult too thus, increasing the overall verification time. Using the proposed approach, the functional errors can be detected and corrected at an early design stage so that when designing adiabatic circuits at the transistor level, the circuit performs correctly and the time for debugging the errors can substantially be reduced. The function is defined using a library containing the behavioral VHDL models of adiabatic domino XOR logic gate. Finally, this library is used to develop and verify the structural VHDL representation of a full adder, as a design example that demonstrates the practicality of the proposed approach. This paper proposes a VHSIC Hardware Descriptive Language (VHDL) based modelling approach for developing models representing single phase adiabatic logic designs.

Keywords- Adiabatic logic, domino, low power, XOR, adder and VHDL
Publication Details
Unique Identification Number - IJEDR2001024
Page Number(s) - 125-130
Pubished in - Volume 8 | Issue 1 | January 2020
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Shiwani Singh,  Sonam Rathore,   "Adiabatic Logic Modelling using VHDL", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.8, Issue 1, pp.125-130, January 2020, Available at :
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