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Paper Details
Paper Title
Area-Efficient 128-bit Carry Select Adder Architecture
Authors
  Srinivasareddy B,  D.Manjularani
Abstract
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed design in terms of area, power. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.
Keywords- Application specific integrated circuit (ASIC), area-efficient,CSLA, low power
Publication Details
Unique Identification Number - IJEDR1401037Page Number(s) - 210-214Pubished in - Volume 2 | Issue 1 | March 2014DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Srinivasareddy B,  D.Manjularani ,   "Area-Efficient 128-bit Carry Select Adder Architecture", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 1, pp.210-214, March 2014, Available at :http://www.ijedr.org/papers/IJEDR1401037.pdf
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