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ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Design and Verification of Asynchronous Five Port Router for Network on Chip
  Ms. J.Ujwala,  Dr. Rangaiah Leburu

Multiprocessor system on chip is rising as a replacement trend for System on chip style however the wire and power style constraints square measure forcing adoption of recent style methodologies. Researchers pursued a ascendable answer to the current downside i.e. Network on Chip (NOC). Network on chip design higher supports the combination of SOC consists of on chip packet switched network. so the thought is borrowed from massive scale multiprocessors and wide space network domain and envisions on chip routers primarily based network. Cores access the network by means that of correct interfaces and have their packets forwarded to destination through multichip routing path. so as to implement a competitive operative design, the router ought to be expeditiously style because it is that the central element of operative design .Design and simulation of five Port Router was designed and its simulation was through with ModelSim6.5e and synthesis victimization Xilinx Ise10.1i.

Keywords- NOC, SOC
Publication Details
Unique Identification Number - IJEDR1403056
Page Number(s) - 3156-3160
Pubished in - Volume 2 | Issue 3 | Sept 2014
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Ms. J.Ujwala,  Dr. Rangaiah Leburu ,   "Design and Verification of Asynchronous Five Port Router for Network on Chip", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 3, pp.3156-3160, Sept 2014, Available at :http://www.ijedr.org/papers/IJEDR1403056.pdf
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