Testing of RAM's Through Symmetric Transparent Online BIST

  Jammana Sreekanth Reddy,  K. Bala Chandra,  T Lalith Kumar.

Transparent BIST schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric Transparent Built-in Self Test (BIST) schemes skip the signature prediction phase required in traditional transparent BIST, achieving considerable reduction in test time. Previous works on both offline MARCH-C testing scheme and online testing symmetric transparent BIST schemes require that a separate BIST module is utilized for each RAM under test. This approach, given the large number of memories available in current chips, increases the hardware overhead of the BIST circuitry. In this paper we propose a Symmetric transparent online BIST scheme that is used to test RAMs of different word widths; hence, more than one RAMs can be tested in a roving manner and here in this paper we are testing 5 RAMs of word lengths 3 bit to 7 bit . The hardware used for proposed scheme is smaller compared to the previously utilized proposed symmetric transparent schemes, for typical memory configurations.

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Unique Identification Number - IJEDR1404009
Page Number(s) - 3412-3416
Pubished in - Volume 2 | Issue 4 | Dec 2014
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Jammana Sreekanth Reddy,  K. Bala Chandra,  T Lalith Kumar.,   "Testing of RAM's Through Symmetric Transparent Online BIST", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 4, pp.3412-3416, Dec 2014, Available at :http://www.ijedr.org/papers/IJEDR1404009.pdf